Инженер-разработчик ASIC / FPGA (RTL, Verilog)

About Actogram

Actogram is a technology startup developing algorithms that transform wearable sensor data into meaningful insights into biological rhythms, sleep, and long-term health.

One of our core technology directions is designed for integration into traditional quartz watches, enabling continuous biological rhythm tracking while maintaining multi-year operation from a coin-cell battery.

We are looking for a Digital ASIC / RTL Engineer to become the technical owner of the algorithm-to-silicon process and lead the development of an ultra-low-power ASIC implementation of the Actogram algorithm.

The main objective is to produce a silicon-proven Actogram IP Core through an MPW program and prepare a reusable semiconductor IP package for licensing and integration into third-party watch ASICs and SoCs.

Responsibilities

• Translate the existing Actogram algorithm into a synthesizable ultra-low-power digital architecture

• Define the ASIC architecture and implement RTL

• Perform functional verification against the reference algorithm

• Perform synthesis and preliminary Power, Performance and Area (PPA) assessment

• Define clocking, power management, memory and sensor/Wake-on-Motion interfaces

• Prepare the design for physical implementation and MPW tape-out

• Coordinate with external ASIC design, foundry/MPW, packaging and testing partners where required

• Lead bring-up and validation of the fabricated silicon.

• Measure and document actual power consumption and functional performance

• Design the MPW prototype for post-silicon functional and power characterization, including dedicated test modes, controllable clocking, observable internal states and isolated power measurement capability

• Prepare the resulting architecture, RTL, verification environment and implementation documentation as a reusable licensable semiconductor IP package suitable for integration into third-party watch ASICs and SoCs

Requirements

• 5+ years of experience in digital ASIC/SoC design, with experience in digital ASIC architecture, not only FPGA development

• Strong proficiency in SystemVerilog, Verilog and/or VHDL

• Experience translating algorithms from C/C++, pseudocode or mathematical specifications into hardware architecture and RTL

• Ability to design datapath and control logic/FSM, registers, counters, timers, accumulators, comparators and simple memory architectures

• Experience implementing algorithms using fixed-point, integer and Boolean logic without an FPU

• Hands-on experience with ultra-low-power digital design, including clock gating, power gating, duty cycling, event-driven architecture, always-on domains and sleep/wake logic

• Experience designing extremely low-power always-on digital logic intended to operate continuously in coin-cell-powered devices

• Understanding of power budgeting at the μW/μA level and the ability to identify which architectural blocks will dominate power consumption

• Experience with always-on sensor processing, preferably accelerometer, motion or Wake-on-Motion

• Experience with RTL simulation, verification and synthesis, for example Questa/ModelSim, Verilator, Synopsys, Cadence or Siemens flows

• Ability to perform preliminary Power, Performance and Area (PPA) analysis

• Understanding of the complete ASIC flow: RTL → synthesis → STA → place & route → sign-off → tape-out, even if physical design is performed by another specialist

• Ability to act as the technical owner of the complete algorithm-to-silicon process, including coordination with external design and manufacturing partners

• English sufficient for independent technical communication with international partners

Nice to have

• Knowledge of low-power standards such as UPF/CPF

Conditions

• Remote work

• International team

• We plan to start with a part-time role, with a transition to full-time within 2–3 months

• Compensation for full-time employment: from $4000 per month

Final compensation is discussed individually depending on experience and level of technical ownership.